Silicon CMOS image sensors for imaging from infrared to soft x-rays are known. FIGS. 1 to 3 show equivalent circuit diagrams of known silicon CMOS image sensors using a photodiode, a pinned photodiode and photogate respectively, in which T1 is a reset transistor, T2 is a source follower, T3 is a row select transistor and T4 is a transfer gate. FIGS. 4 to 7 show corresponding cross-sections of known CMOS image sensors using a photodiode, a buried photodiode, a pinned photodiode and photogate respectively.
However, to form near-infrared images it is desirable to use a relatively thick silicon active layer, e.g. 100-200 μm, to provide sufficient absorption depth for the infrared radiation. It is known to apply a reverse bias across an active layer of CMOS image sensors to reduce crosstalk and improve quantum efficiency. However, because of the low operating voltages of CMOS image sensors, achieving full depletion can be very difficult for thick active layers e.g. over >20 μm and requires additional reverse biasing of the substrate. The thickness of an active layer of a CMOS image sensor is determined by the available voltage and silicon resistivity. For the highest available resistivity in CMOS currently available of approximately 1,000 ohm·cm for epi and with a 3.3V supply, a “thick” active layer means an active layer with a thickness that cannot be depleted under normal operating voltages—this corresponds to a thickness >20 μm or thereabouts. That is, currently full depletion with a 3.3V diode bias can be obtained only up to a thickness of approximately 18 μm with epi. In the case of bulk silicon the highest available resistivity is 10,000 ohm·cm and this could deplete up to around 50 microns. In either case, for greater thicknesses, depletion regions may be formed only under the photodiodes which would decrease quantum efficiency and cause crosstalk due to charge diffusion and slow charge collection. The applied reverse bias voltage may then cause a parasitic current to flow through the active layer around the depletion regions.
Referring to the cross-section of a known CMOS image sensor 10 shown in FIG. 8, the CMOS image sensor 10 comprises a p-epitaxial or bulk silicon active layer 11 on a p+ substrate or backside contact respectively 12, and pixels 20, each comprising CMOS active components (not shown) in a p well 21 and a photodiode with an n+ well 22 in a front side of the p-epitaxial or bulk silicon layer 11. The image sensor further comprises a guard ring n+ well 23 surrounding the pixels 21 and, if there is no backside bias contact, a substrate bias p+ well 24 on the front side at a distance A from the guard ring n+ well 23 greater than a thickness D of the image sensor 10 (it will be noted that FIG. 8 is not shown to scale).
Under the influence of the negative bias voltage, typically higher than −10V in absolute value, a current may flow through a resistive path 13 from the p wells 21 to the p+ substrate or backside contact 12. However, in use depletion regions 14, 15, 16 are formed in the active layer below the respective photodiode n+ wells 22, and these depletion regions may, in some circumstances, spread laterally below the p wells 21 to pinch off the current between the p wells 21 and the p+ backside contact 12 as shown in respect of depletion regions 14 and 15 but not in respect of depletion regions 15 and 16. Referring to FIG. 9, with some structures and operating conditions the depletion regions 15 and 16 form pinch-off 17 whereas under other conditions, for example when the photodiode has collected a charge under irradiation, the depletion region 15′ may be smaller than depletion region 15 and no pinch-off occurs between depletion regions 15′ and 16, allowing a parasitic current to flow.
As shown in FIGS. 10 and 11, the extent of the overlap of the depletion regions creating the pinch-off is dependent on relative doping levels and depths of the p-wells and n-wells. Referring to FIG. 10, with identically doped p wells 211 and n wells 221 of equal depth, and with the width Lnw of the n well 221 greater than a width Lpw of the p well 211, the depletion regions 151 and 161 may overlap to form a pinch off 171. Referring to FIG. 11, with identically doped p wells 212 and n wells 222 but with the n wells 222 deeper and wider than the p wells 212, a greater overlap may occur between neighbouring depletion regions 142, 152 and 162 to form wider pinch-offs 172.
Thus, a pinch-off 17 cannot be achieved under all operating conditions and may not be possible if the wells are deep or more highly doped than the photosensitive elements.
Although these effects have been described in a CMOS image sensor with a p-type substrate, it will be understood that the same effects occur in a CMOS image sensor with opposite conductivity type layers and wells.
US 2005/0139752 discloses a front-illuminated CMOS sensor in which a back bias voltage is varied to vary a width of a depletion area in the photodiode to adjust the sensitivity of the sensor to red, green and blue light without using a colour filter. The CMOS sensor has a photodiode region and a transistor region. An n-type buried layer, which may be horizontal or U-shaped, is formed in the p-type substrate below the transistor region to prevent the bias voltage affecting the transistor region.
US 2008/0217723 discloses a back-illuminated CMOS sensor with a pinned photodiode to collect charge carriers formed in the 5μ thick silicon substrate. In sensors in which reverse bias is applied a triple well may be provided below the transistor region so that the voltage applied to the transistors is unaffected by the bias voltage. In addition, a p-type buried layer beneath the transistor region may be provided to reflect charge carriers generated in the p-doped silicon substrate away from the transistor region and towards the photodiode region.
US 2011/024808 discloses a back-illuminated CMOS sensor with a deep n-well in a p-substrate beneath a CMOS logic region to generate a barrier for substrate bias. An n-well surrounding the pixels forms a depletion region around the edge of the pixels to ensure that the pixels pinch off substrate bias in proximity to a p+ return contact. To achieve substantially full depletion of the p-type epitaxial silicon layer, the layer may be of intrinsic silicon or lightly doped. A reverse bias voltage applied to a front contact causes a depletion region to extend to the full substrate thickness below the pixels.
There remains a requirement for an efficient method of preventing parasitic substrate current with a thick CMOS image sensor device structure formed with a minimum of processing steps.